NAND flash is currently the most prominent non-volatile semiconductor memory technology, used mostly for storage. Both flash and phase-change memory employ multi-level cells (MLC), while beneficial in terms of storage capacity and cost per bit, MLC comes at a performance penalty. The technology presented is an innovative memory architecture, composed of encoder, decoder and address-to-cells mapping. The technology improves the best known average page write time, has an accelerated read time, and is proven to achieve the upper bound of write speed. The proposed scheme does not require data redundancy, reduces energy consumption and is suitable to every product that employs flash or phase change memory.